1. Field of the Invention
The invention relates in general to a method of fabricating a metal-oxide semiconductor (MOS) capacitor. More particularly, this invention relates to a method of fabricating a MOS capacitor on a doped region with the same dopant conductive type.
2. Description of the Related Art
In semiconductor fabrication, complementary metal-oxide semiconductor (CMOS) integrated circuit is a well known design. The CMOS device typically includes many p-type MOS transistors and n-type MOS transistors, which are formed in the corresponding wells in a substrate. Particularly, a dual-well design in CMOS includes wells with two conductive types, usually formed next to each other. The CMOS device needs not only the MOS transistors but also a capacitor. The capacitor usually is a MOS capacitor known in the conventional technologies as being disclosed in U.S. Pat. No. 5,703,806 and U.S. Pat. No. 5,168,075. However, the conventional MOS capacitor has some drawbacks due to its depletion effect in semiconductor materials, which affects performance of the CMOS device. A stable capacitance can only be achieved under small bias.
The conventional MOS capacitor typically only uses the overlapping region between the source/drain region and the gate electrode. This also causes additional fabrication process for photomask and implantation. The MOS capacitor is also incorporated in, for example, a mix mode circuit, where a dedicated capacitor with specific processes is further employed.
In a conventional MOS capacitor, the source and drain regions are shorted with each other as an electrode. The gate of the MOS transistor is used as the other electrode of the capacitor, while the gate oxide layer is used as the capacitor dielectric. FIG. 1A depicts a conventional N-type (NMOS) capacitor structure built in a P-well of a complementary metal-oxide semiconductor (CMOS) integrated circuit. Likewise, a P-type MOS (PMOS) capacitor is conventionally formed in an N-well. In FIG. 1A, generally, a MOS transistor includes a gate electrode typically having a gate oxide layer 106, a polysilicon layer 108, and a silicide layer 110. On the sidewall of the gate electrode, a spacer 112 is also formed. Under the spacer 112, an source/drain extension region 116 is formed in the substrate 100 at the well 104. The source/drain region 114 is formed in the substrate 100, with respect to the well 104, at each side of the gate electrode. For another well 105, another MOS transistor is accordingly formed. A conventional MOS capacitor is similar to a MOS transistor but the operation is different.
For the use as a capacitor, an additional implantation with the same conductive type as the well 104 under the gate oxide layer 106 is formed, so as to have lower bias on the capacitor.
Various capacitors exist in the conventional MOS capacitor of FIG. 1A. For example, the capacitors exists in the NMOS capacitor is depicted in FIG. 1B. A capacitor 118 exists between the gate oxide layer 106 and the polysilicon layer 108, resulting from the depletion effect. A capacitor 120 exists between the polysilicon layer 108 and the well 104 in the semiconductor substrate, the gate oxide layer 106 serves as the dielectric of the capacitor. If the well 104 is taken as one electrode of the capacitor, a capacitor 122 also exists near the interface between the gate oxide layer 106 and the well 104 of the substrate, due to depletion effect also. If the source/drain region is taken as one electrode, a capacitor 124 also exists between the polysilicon layer 108 and the source/drain region.
Moreover, the silicide layer 110 on top of the gate has its specific function. FIG. 1C is a top view, schematically illustrating MOS devices formed on the wells. When the MOS devices are formed in the wells with different conductive type. For example, a P well and an N well are typically formed abutting each other. A diode inherently exists between the well. In order to have proper connection between the MOS devices with being affected by the substrate diode effect, the silicide layer 110 is formed to connect the MOS devices. From the cross-section view, the silicide 110 is shown in FIG. 1A.
For the MOS device as shown in FIG. 2, an oxide layer O and a metal layer M are sequentially formed on a semiconductor substrate S, such as a P-type silicon substrate with a ground voltage. The gate voltage Vg can be applied on the metal M. The MOS device is also like a capacitor. When voltage Vg is zero or less than zero, holes are accumulated near the substrate surface under the oxide O. This is usually called as an accumulation mode. If the voltage is negative up to a certain level, the capacitance is about fixed. When voltage Vg is applied with higher quantity, a strong inversion starts to occur on the semiconductor surface. The minimum voltage to cause the strong inversion is called as the flat-band voltage. The flat-bang voltage depends on a work function of the semiconductor substrate. When the voltage Vg is greater than the flat-band voltage but is still not sufficiently high, a depletion phenomenon occurs, at which the holes are expelled in opposite direction and leaves a negative charge near the he substrate surface under the oxide O. A depletion capacitor then occurs. When the gate voltage Vg is great than a threshold voltage, the strong inversion completely occurs on the semiconductor surface under the oxide 0. For the MOS device, the threshold voltage is the bias level for the gate voltage to turn on the MOS device.
FIG. 3 shows a conventional drain current in a MOS transistor versus a drain voltage, with respect to different threshold voltage VT. When the MOS device is turned on by applying the gate voltage greater than the threshold voltage, the drain current Id achieves a stable current when drain voltage Vd is greater than a certain quantity. However, when the drain voltage is small, a linear region occurs. The linear region provides applications for the MOS device.
In general, the MOS capacitor as shown in FIG. 1B can be operated in three modes:
1. When a gate bias is sufficiently high, that is, higher than the threshold voltage in MOS transistor operation, a two dimensional electron gas is generated near the substrate/oxide interface referred as an inversion layer. The electrons in the inversion layer are conducted to electrodes through the N+ implanted source/drain regions. In this operation mode, a high quality fixed capacitance from the gate oxide layer 106 is provided.
2. When the gate bias voltage is between the threshold voltage and a flat-band voltage, certain depth of the substrate is depleted under the gate electrode, and thus forming a variable capacitor 122. Usually, the lightly doped P-type (Pxe2x88x92) substrate electrode is not connected through the heavily doped N-type (N+) source/drain regions, a high series resistance occurs with the substrate picking up the connection certain distance away. This operation mode is called the depletion mode operation.
3. When the gate bias voltage is below the flat-band voltage, the hole accumulates under the gate electrode and this mode of operation also experiences higher series resistance while trying to connect the Pxe2x88x92 substrate electrode through well pickup contact.
For the conventional MOS capacitor, when the capacitor is set under the depletion mode, it has several disadvantages. In this situation, the conventional MOS capacitor experiences high series resistance in depletion mode since one of the capacitor electrodes is the substrate, which has to be picked up through the substrate contact at certain distance away. The high series resistance gives rise the effects of:
1. The RC time constant of the MOS capacitor and this parasitic resistor gives the a low-pass frequency response limiting the applicable frequency range of the MOS variable capacitor structure; and
2. Even within the applicable frequency range of this MOS variable capacitor structure, a higher parasitic resistance gives rise to higher signal power loss and hence results in a lower quality factor.
A method of fabricating a metal-oxide semiconductor (MOS) capacitor in a complementary MOS fabrication process with dual-doped poly gates, the method comprising providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type. A dielectric layer is formed on the substrate. A first poly gate of the first conductive type is formed on the dielectric layer over the first well and a second poly gate of the second conductive type is formed on the dielectric layer over the second well. A first doped region of the first conductive type is formed in the substrate at each side of the first poly gate. A second doped region of the second conductive type is formed in the substrate at each side of the second poly gate layer. A spacer is formed on sidewalls of the first poly gate and the second poly gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region. An implantation is performed on the exposed portion of the first doped region with dopants of the first conductive type, so as to form a first substrate electrode. An implantation process is performed on the exposed portion of the second doped region with dopants of the second conductive type to form a second substrate electrode.
In the foregoing, a first channel region in the first well under the first poly gate is implanted by dopants of the first conductive type, so as to form a first channel implantation region. A second channel region in the second well under the second poly gate is implanted by dopants of the second conductive type, so as to form a second channel implantation region. The channel implantation regions can reduce the applied electrode bias of the MOS capacitor.
In the depletion mode operation, the substrate electrode is directly connected to the doped regions through the channel implantation region with resistivity much lower than well resistance experienced by the conventional structure.
The invention further provides a MOS capacitor with a gate used as an electrode, the gate oxide layer used as a capacitor dielectric, and a substrate doped region used as the other electrode of the capacitor. The substrate doped region is formed in the substrate at each side of the gate electrode like a source/drain region for a MOS transistor but the conductive type is different. The substrate doped region has the same conductive type as that of the substrate.
The foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.